Files: 5 Total size: 2.4 GB Total requests: 10 Last access time: 14 hours, 8 minutes
|
|
Mehta A. Introduction to SystemVerilog 2021
3 months, 3 weeks
Files: 1 Total size: 26.2 MB Total requests: 73 Last access time: 1 week, 1 day
|
|
Логическое проектирование на SystemVerilog - Дональд Томас - 2019.pdf
11 months, 2 weeks
Files: 1 Total size: 42.9 MB Total requests: 71 Last access time: 2 weeks
|
Files: 1 Total size: 5.2 MB Total requests: 95 Last access time: 5 days, 12 hours
|
Files: 3 Total size: 11.9 MB Total requests: 172 Last access time: 4 days, 2 hours
|
|
Дональд Томас - Логическое проектирование и верификация систем на SystemVerilog - 2019.pdf
1 year, 2 months
Files: 1 Total size: 4.5 MB Total requests: 968 Last access time: 7 hours, 52 minutes
|
|
Learn SystemVerilog Assertions and Coverage Coding in-depth
1 year, 9 months
Files: 5 Total size: 745.0 MB Total requests: 875 Last access time: 3 hours, 25 minutes
|
|
Sutherland S. Verilog and SystemVerilog Gotchas...2007
2 years, 4 months
Files: 1 Total size: 6.6 MB Total requests: 221 Last access time: 3 hours, 27 minutes
|
|
SystemVerilog Beginner Write Your First Design &TB Modules
2 years, 4 months
Files: 4 Total size: 448.2 MB Total requests: 147 Last access time: 1 month, 2 weeks
|
|
SystemVerilog Design Start Programming Your Own ICs in HDL
2 years, 5 months
Files: 3 Total size: 540.1 MB Total requests: 325 Last access time: 5 days, 18 hours
|